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RNA50C27AUS
CMOS System-Reset IC
REJ03D0834-0100 Preliminary Rev.1.00 Apr 10, 2006
Description
This IC facilitates complicated power-on and power-monitoring resets of microcomputers that require the 3.3-V and 1.8-V dual power supplies. It also facilitates change of delay time of reset signal by externally setting resistance and capacity for delay time. By employing complementary open-drain output, desired output such as open-drain output and CMOS output can be obtained.
Functions
* * * * * * 3.3-V detection voltage Accuracy of 3.3-V detection voltage Hysteresis of 3.3-V detection voltage Open-drain/CMOS output 1.8-V PMOS drive output Ultra-small SSOP-8 package : 2.7 V : 1.0% : 5% Typ.
Block Diagram
MR 8 VDD33 1
- +
CRext 7
2 RESP Delay 3 RESN
Vref VDD18 6 5 SWG GND 4
Rev.1.00 Apr 10, 2006 page 1 of 7
RNA50C27AUS
Pin Arrangement
VDD33 RESP RESN GND 1 2 3 4 (Top view) 8 7 6 5 MR CRext VDD18 SWG
Pin Description
Pin No. 1 2 3 4 5 6 7 Pin Name VDD33 RESP RESN GND SWG VDD18 CRext Function Input power supply pin for 3.3-V voltage. Recommended operating range is 2.7 to 3.6 V. Set the input voltage to 0.033 V/s or less when starting up. Active-low reset signal output pin. By connecting to RESN pin, CMOS output can be used. If using open-drain, please connect pull-down resistor. Active-low reset signal output pin. By connecting to RESP pin, CMOS output can be used. If using open-drain, please connect pull-up resistor. GND pin External PMOS gate control signal to be set between 1.8-V power supply and 1.8-V voltage input of microcomputer. Input power supply pin for 1.8-V voltage. Recommended operating range is 1.65 to 3.6 V. Connecting pin for Rext resistance and Cext capacity that determine the delay time of reset signal. 3.3 k or more is recommended for resistance. The delay time, tDLY, is given by the following formula.
tDLY = Cext x Rext [s]
8 MR Pin to provide reset manually. MR pin is pulled-up to VDD33 through internal resistor.
Rev.1.00 Apr 10, 2006 page 2 of 7
RNA50C27AUS
Absolute Maximum Ratings
Item Supply voltage Input voltage Output voltage Input current Output current Supply current Power dissipation Storage temperature Symbol VDD33 VDD18 VI VO II IO IDD PT Tstg Ratings 4.6 4.6 -0.3 to VDD33+0.3 -0.3 to VDD33+0.3 20 25 25 273 -55 to +125 Unit V V V mA mA mA mW C
Recommended Operating Conditions
Item Supply voltage Input voltage Output voltage External resistor External capacitor Drivable capacitor Operating temperature Symbol VDD33 VDD18 VMR VO VOSWG Rext Cext CL Ta Min VTH33 1.65 0 0 0 3.3 -- -- -40 Typ -- -- -- -- -- -- No limit 2200 -- Max 3.6 VDD33 VDD33 VDD33 VDD18 -- -- -- 85 Unit V V V k pF C VDD33 = 3.3 V SWG output Remarks
Rev.1.00 Apr 10, 2006 page 3 of 7
RNA50C27AUS
Electrical Characteristics
DC Characteristics (VDD33 = 3.3 V, VDD18 = 1.8 V, Ta = 25C, CRext:R = 10 k)
Item Quiescent supply current Detection voltage Symbol IDD33 IDD18 VTH33 VTHH VTHL Detection voltage temperature dependency Detection voltage hysteresis MR Low-level input voltage High-level input voltage internal pull-up resistance CMOS *1 RESP RESN SWG Low-level output current High-level output current Output leakage current Output leakage current High-level output voltage Output source current Low-level output voltage Output sink current Min 0.75 0.25 Typx0.99 1.2 -- -- VTH33x3% -- VTH33x0.75 -- 7.5 5 -- -- 1.7 1.5 -- 0.2 Typ 1.5 0.5 2.7 -- -- 100 VTH33x5% -- -- T.B.D. 15 10 -- -- -- 3 -- 0.35 Max 4 2 Typx1.01 -- 0.55 -- VTH33x8% VTH33x0.25 -- -- 30 20 0.1 0.1 -- 6 0.1 0.55 A A V mA V mA ppm/C V V V k mA VO = 0.5 V VO = VDD33 - 0.5 V RESN off RESP off VO = open VO = VDD33 - 0.5 V VO = open VO = 0.5 V V Unit A Test Conditions All outputs are open
Vth33 VthTa
VHYS VIL VIH RMR IOL IOH ILEAK ILEAK VOH IOH VOL IOL
Note: When the voltage within VIL < VIN < VIH is applied to MR and VDD18 input by DC, oscillation may occur. 1. When RESP output and RESN short out and CMOS output is used.
AC Characteristics
Item RESP Propagation delay time Response time RESN Propagation delay time Response time SWG Propagation delay time Response time Delay time Symbol tpLH tpHL tr tf tpLH tpHL tr tf tpLH tpHL tr tf tDLY Min -- -- -- -- -- -- -- -- -- T.B.D. T.B.D. T.B.D. -- Typ 50 5 5 5 50 1.5 5 5 50 1.5 1.0 7.6 93 Max 400 T.B.D. T.B.D. T.B.D. 400 T.B.D. T.B.D. T.B.D. 400 T.B.D. T.B.D. T.B.D. -- ms CRext:C = 0.1 F, R = 1 M s s ns s CL = 2200 pF ns s s CL = 15 pF, CRext:C = open CL = 15 pF Unit s Test Conditions CL = 15 pF, CRext:C = open CL = 15 pF
Rev.1.00 Apr 10, 2006 page 4 of 7
RNA50C27AUS
Timing Chart
VDD33
VREL VTH33 VOPmin
VDD18
VTH18
MR
RES
tDLY
tDLY
tDLY
tDLY
tDLY
tDLY
SWG
Rev.1.00 Apr 10, 2006 page 5 of 7
RNA50C27AUS
Package Dimensions
JEITA Package Code P-VSSOP8-2.3x2-0.50 RENESAS Code PVSP0008KA-A Previous Code TTP-8DB/TTP-8DBV MASS[Typ.] 0.010g
D 1.5 0.2 8 5 F
bp b1
c1 HE E
Terminal cross section
c
1 e
4 bp
( 0.17 )
L1
Reference Dimension in Millimeters Symbol
Detail F
Min Nom Max D 1.8 2.0 2.2 E 2.2 2.3 2.4 A2 0.6 0.7 0.8 A1 0.1 0 A bp 0.15 0.22 0.3 b1 0.20 c 0.08 0.13 0.23 c1 0.11 HE 2.8 3.1 3.4 e (0.5) x y Z L L1 (0.4)
Footprint
0.5 0.5 0.5 Unit: mm
A1
A2
0.3
SSOP-8 Footprint Example Note: These numbers on the diagram are reference values. Please adjust size, space, and other area of footprint as needed.
Rev.1.00 Apr 10, 2006 page 6 of 7
0.2
0.4
0.1
3.1
2.3
RNA50C27AUS
Taping and Reel Specifications
[Taping] W 8 P1 4 A0 2.25 B0 3.4 4 K0 K0 1.0 2 F 3.5 1.5 D1 1.05 Maximum Storage No. 3,000 IC/Reel
1.75
Unit: mm
Reel Type C
Packing Form Non dry pack
The pin1 is located in the hatching portion
B0
F W
A0 0.3 P1 D1
Reel off direction
[Reel] Tape width: W 8
Reel type: C W1 13.0 W2 9.0
12 0
W1
2.0 0.5
13 0.5
4 0.5
W2
Rev.1.00 Apr 10, 2006 page 7 of 7
178 2
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